#
# System signal
#
set_property PACKAGE_PIN G20 [get_ports led]
set_property IOSTANDARD LVCMOS33 [get_ports led]
#set_property PACKAGE_PIN G21 [get_ports led[1]]
#set_property IOSTANDARD LVCMOS33 [get_ports[1]]
set_property PACKAGE_PIN M21 [get_ports clk_osc]
set_property IOSTANDARD LVCMOS33 [get_ports clk_osc]
#set_property PACKAGE_PIN H7 [get_ports sys_rst_n]
#set_property IOSTANDARD LVCMOS33 [get_ports sys_rst_n]

#
# SDRAM signals
#
set_property PACKAGE_PIN G22 [get_ports sdram_clk]
set_property IOSTANDARD LVCMOS33 [get_ports sdram_clk]
set_property PACKAGE_PIN H22 [get_ports sdram_cke]
set_property IOSTANDARD LVCMOS33 [get_ports sdram_cke]

set_property PACKAGE_PIN K23 [get_ports {sdram_dqm[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dqm[1]}]
set_property PACKAGE_PIN J25 [get_ports {sdram_dqm[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dqm[0]}]

set_property PACKAGE_PIN K25 [get_ports sdram_casn]
set_property IOSTANDARD LVCMOS33 [get_ports sdram_casn]
set_property PACKAGE_PIN K26 [get_ports sdram_rasn]
set_property IOSTANDARD LVCMOS33 [get_ports sdram_rasn]
set_property PACKAGE_PIN J26 [get_ports sdram_wen]
set_property IOSTANDARD LVCMOS33 [get_ports sdram_wen]
set_property PACKAGE_PIN L25 [get_ports sdram_csn]
set_property IOSTANDARD LVCMOS33 [get_ports sdram_csn]

set_property PACKAGE_PIN M26 [get_ports {sdram_ba[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_ba[1]}]
set_property PACKAGE_PIN M25 [get_ports {sdram_ba[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_ba[0]}]

set_property PACKAGE_PIN J21 [get_ports {sdram_addr[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_addr[12]}]
set_property PACKAGE_PIN K22 [get_ports {sdram_addr[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_addr[11]}]
set_property PACKAGE_PIN R25 [get_ports {sdram_addr[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_addr[10]}]
set_property PACKAGE_PIN K21 [get_ports {sdram_addr[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_addr[9]}]
set_property PACKAGE_PIN L22 [get_ports {sdram_addr[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_addr[8]}]
set_property PACKAGE_PIN L23 [get_ports {sdram_addr[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_addr[7]}]
set_property PACKAGE_PIN L24 [get_ports {sdram_addr[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_addr[6]}]
set_property PACKAGE_PIN M22 [get_ports {sdram_addr[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_addr[5]}]
set_property PACKAGE_PIN M24 [get_ports {sdram_addr[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_addr[4]}]
set_property PACKAGE_PIN N26 [get_ports {sdram_addr[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_addr[3]}]
set_property PACKAGE_PIN P26 [get_ports {sdram_addr[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_addr[2]}]
set_property PACKAGE_PIN P25 [get_ports {sdram_addr[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_addr[1]}]
set_property PACKAGE_PIN R26 [get_ports {sdram_addr[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_addr[0]}]

set_property PACKAGE_PIN D25 [get_ports {sdram_dq[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[0]}]
set_property PACKAGE_PIN D26 [get_ports {sdram_dq[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[1]}]
set_property PACKAGE_PIN E25 [get_ports {sdram_dq[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[2]}]
set_property PACKAGE_PIN E26 [get_ports {sdram_dq[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[3]}]
set_property PACKAGE_PIN F25 [get_ports {sdram_dq[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[4]}]
set_property PACKAGE_PIN G25 [get_ports {sdram_dq[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[5]}]
set_property PACKAGE_PIN G26 [get_ports {sdram_dq[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[6]}]
set_property PACKAGE_PIN H26 [get_ports {sdram_dq[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[7]}]
set_property PACKAGE_PIN J24 [get_ports {sdram_dq[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[8]}]
set_property PACKAGE_PIN J23 [get_ports {sdram_dq[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[9]}]
set_property PACKAGE_PIN H24 [get_ports {sdram_dq[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[10]}]
set_property PACKAGE_PIN H23 [get_ports {sdram_dq[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[11]}]
set_property PACKAGE_PIN G24 [get_ports {sdram_dq[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[12]}]
set_property PACKAGE_PIN F24 [get_ports {sdram_dq[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[13]}]
set_property PACKAGE_PIN F23 [get_ports {sdram_dq[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[14]}]
set_property PACKAGE_PIN E23 [get_ports {sdram_dq[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[15]}]

# uart
set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33} [get_ports {uart_rx[0]}]
set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {uart_tx[0]}]

set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS33} [get_ports spi_cen0]
set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS33} [get_ports spi_sio0_si_mosi0]
set_property -dict {PACKAGE_PIN M5 IOSTANDARD LVCMOS33} [get_ports spi_sio1_so_miso0]
set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS33} [get_ports spi_sclk0]

# J10
set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports {gpio[0]}]
set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS33} [get_ports {gpio[1]}]
set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS33} [get_ports {gpio[2]}]
set_property -dict {PACKAGE_PIN G8 IOSTANDARD LVCMOS33} [get_ports {gpio[3]}]
set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS33} [get_ports {gpio[4]}]
set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS33} [get_ports {gpio[5]}]
set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS33} [get_ports {gpio[6]}]
set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports {gpio[7]}]

# J11
#set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports {gpio[9]}]
#set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports {uart_rx[1]}]
#set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS33} [get_ports {uart_tx[1]}]
set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports audio_r]
set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports audio_gain]
set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS33} [get_ports audio_l]
set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS33} [get_ports audio_shutdown]
set_property PULLTYPE PULLUP [get_ports {audio_gain}]
set_property PULLTYPE PULLUP [get_ports {audio_shutdown}]

# J13
#set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS33} [get_ports audio_r]
#set_property -dict {PACKAGE_PIN N21 IOSTANDARD LVCMOS33} [get_ports audio_gain]
#set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS33} [get_ports audio_l]
#set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS33} [get_ports audio_shutdown]
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS33} [get_ports {gpio[9]}]
set_property PULLTYPE PULLUP [get_ports {gpio[9]}]
set_property -dict {PACKAGE_PIN N21 IOSTANDARD LVCMOS33} [get_ports {uart_rx[1]}]
set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS33} [get_ports {uart_tx[1]}]

# J14
set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS33} [get_ports spi_cen1]
set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS33} [get_ports spi_sio0_si_mosi1]
set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS33} [get_ports spi_sio1_so_miso1]
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS33} [get_ports spi_sclk1]
set_property -dict {PACKAGE_PIN N24 IOSTANDARD LVCMOS33} [get_ports {gpio[8]}]
set_property PULLTYPE PULLUP [get_ports {gpio[8]}]


set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]

#create_clock -period 20.000 -name clk_osc -waveform {0.000 10.000} -add
create_clock -add -name clk_osc -period 20.000 -waveform {0.000 10.000} [get_ports clk_osc]


set_property DRIVE 16 [get_ports spi_sclk0]
set_property DRIVE 16 [get_ports spi_sclk1]
set_property DRIVE 16 [get_ports spi_sio0_si_mosi0]
set_property DRIVE 16 [get_ports spi_sio0_si_mosi1]
set_property DRIVE 16 [get_ports spi_sio1_so_miso0]
set_property DRIVE 16 [get_ports spi_sio1_so_miso1]
set_property DRIVE 16 [get_ports spi_cen0]
set_property DRIVE 16 [get_ports spi_cen1]

set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
